Description
The 10G SerDes Whitebox IP provides a reusable physical-layer platform for SoCs requiring several high-speed connectivity standards in one compact implementation. Operating from 1.125 Gbps to 10 Gbps, the silicon-proven ST 28FDSOI transceiver supports USB 3.0/3.1, PCIe Gen1/2/3, SATA Gen1/2/3, and JESD204B applications. Programmable transmitter equalization, adaptive receive conditioning, integrated PLL and impedance calibration, eye monitoring, BIST, and loopback functions help simplify high-speed interface integration and validation.
The Whitebox license enables unrestricted reuse and design modification. Customers can adapt the PHY to their protocol mix, optimize PPA, create proprietary derivatives, manage future updates internally, and port the SerDes to another foundry or process node.
Features
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Multi-protocol Tx and Rx SerDes PHY
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Programmable operation from 1.125 Gbps to 10 Gbps
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Supports USB 3.0 and USB 3.1 applications
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Supports PCI Express Gen1, Gen2, and Gen3
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Supports SATA Gen1, Gen2, and Gen3
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Supports JESD204B serial connectivity
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Scalable multi-lane configuration with support for up to four lanes
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Modular platform comprising data and clock slices
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Programmable transmitter amplitude, preemphasis, and slew rate
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Three-tap transmit FIR equalization
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Adaptive receiver equalization Low-power receiver CTLE
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Power-optimized resistive-bridge transmitter
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Integrated PLL and clock-generation functions
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On-chip impedance-calibration capability
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Integrated receiver eye-monitoring support
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USB-oriented OOB and LFPS signalling support
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Built-in self-test, JTAG, and internal loopback modes
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Configurable power/performance operating modes
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Whitebox license with unlimited use, full source
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access, complete modification, and porting rights
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Silicon-proven in ST 28FDSOI
Deliverables
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Verilog behaviour model (A) for simulation
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Liberty (.db/.lib) for synthesis, STA, and equivalence
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checking
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CTL / CTLDB for DFT
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SPF — Standard Test Interface Language (STIL)
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Procedure File — for ATPG
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LEF for APR
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CDL for LVS connection
