Description
The 32G SerDes Whitebox IP provides scalable, high-bandwidth serial connectivity for networking ASICs, communication processors, storage platforms, and data-processing SoCs. The multi-rate Tx/Rx architecture supports legacy rates beginning at 1.125 Gbps and is positioned for operation up to 32 Gbps per lane. Supported applications include CEI-6G/11G, CEI-28G-VSR/MR, XFI/SFI, XAUI/CAUI, SGMII, QSGMII, CR4, and SFP+. Programmable transmit filtering, adaptive receive equalization, clock recovery, and embedded link diagnostics help address a broad range of channel conditions.
Its Whitebox license enables complete architectural customization, unrestricted reuse, internal maintenance, derivative development, and migration to other semiconductor processes. The final qualified rate should be confirmed before publication.
Features
-
Multi-rate transmitter and receiver SerDes PHY
-
Provisional data-rate range of 1.125 Gbps to 32 Gbps per lane
-
Scalable single-lane and multi-lane architecture
-
Supports CEI-6G/11G short-, medium-, and longreach profiles
-
Supports CEI-28G-VSR and CEI-28G-MR
-
Supports XFI and SFI
-
Supports XAUI and CAUI
-
Supports SGMII and QSGMII
-
Supports CR4 and SFP+ applications
-
Programmable transmitter FIR equalization
-
Adaptive receiver CTLE and DFE equalization
-
Robust clock and data recovery
-
Designed for high jitter tolerance and multi-rate clocking
-
Configurable standard parallel interface for PCS or MAC integration
-
Built-in PRBS generation and checking
-
BIST, internal loopback, and eye-monitoring capabilities
-
Power-optimized architecture for low energy per bit
-
Whitebox license with unlimited use, full
-
source/design access, modification, derivative development, and porting rights Silicon-proven in ST 28FDSOI
Deliverables
-
Verilog behaviour model (A) for simulation
-
Liberty (.db/.lib) for synthesis, STA, and equivalence
-
checking
-
CTL / CTLDB for DFT
-
SPF — Standard Test Interface Language (STIL)
-
Procedure File — for ATPG
-
LEF for APR
-
CDL for LVS connection
