Description
The MIPI M-PHY v3.1 Whitebox IP is a silicon-proven, eight-lane receiver PHY for high-bandwidth storage and chip-to-chip connectivity. Supporting Gear 3 High-Speed operation at up to 5.8 Gbps per lane and Low-Speed PWM communication at up to 72 Mbps, the receiver provides an efficient interface for UniPro, UFS, mobile-storage, automotive, and embedded-processing applications. RMMI connectivity, multiple reference-clock options, receiver eye monitoring, and built-in self-test simplify SoC integration, debug, and production validation.
The Whitebox business model supplies the design with unrestricted reuse and modification rights. Customers can customize the eight-lane architecture, optimize its PPA, maintain it independently, create product-specific derivatives, and migrate the PHY to another semiconductor technology.
Features
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Eight-lane MIPI M-PHY receiver architecture
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Target compliance with MIPI M-PHY v3.1
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Receive-only configuration optimized for multilane applications
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Supports HS-MODE Gear 3, Rate A and Rate B
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Data rate of up to 5.8 Gbps per receive lane
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Backward compatibility with lower M-PHY HighSpeed gears
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Supports LS-MODE PWM-G1 through PWM-G4
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Low-Speed data rate of up to 72 Mbps
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Embedded-clock differential signalling
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Receiver clock and data recovery
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RMMI interface for Type-I applications
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Supports 19.2, 26, 38.4, and 52 MHz referenceclock frequencies
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Receiver eye-opening monitoring and debug support
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Built-in self-test for production and final testing
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Low-pin-count and power-efficient architecture
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Suitable for UniPro, UFS, and chip-to-chip communication subsystems
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Whitebox license with unlimited use, complete modification, derivative-development, and porting rights
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Silicon-proven in ST 28FDSOI
Deliverables
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Verilog behaviour model (A) for simulation
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Liberty (.db/.lib) for synthesis, STA, and equivalence
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checking
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CTL / CTLDB for DFT
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SPF — Standard Test Interface Language (STIL)
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Procedure File — for ATPG
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LEF for APR
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CDL for LVS connection
