Description
The I2C/SPI to AHB Bridge Whitebox IP enables an external controller to access internal SoC registers, memories, and peripherals through an I2C or SPI interface. Incoming serial commands are translated into AMBA AHB or AHB-Lite read and write transactions, with configurable addressing, data widths, buffering, error handling, and interrupt generation. Delivered as technology-independent Whitebox RTL, the bridge can be adapted to proprietary command protocols, security requirements, and system-interconnect architectures.
Features
-
Selectable I2C and SPI peripheral-side interfaces
-
AMBA AHB or AHB-Lite initiator interface
-
I2C 7-bit and configurable 10-bit addressing
-
I2C Standard-, Fast-, and Fast-Mode Plus operation
-
Supports I2C START, repeated START, STOP, ACK, and NACK
-
Supports I2C clock stretching
-
SPI clock modes 0, 1, 2, and 3
-
Programmable SPI bit order and transfer length
-
Address-mapped read and write command conversion
-
Configurable 8-, 16-, or 32-bit data handling
-
Optional transaction FIFO buffering
-
Configurable AHB single and burst transfers
-
Error, timeout, status, and interrupt reporting
-
Fully synthesizable Whitebox RTL with complete customization rights
Deliverables
-
Detailed Datasheet
-
Verilog behaviour model (A) for simulation
-
Liberty (.db/.lib) for synthesis, STA, and equivalence
-
checking
-
CTL / CTLDB for DFT
-
SPF — Standard Test Interface Language (STIL)
-
Procedure File — for ATPG
-
LEF for APR
-
CDL for LVS connection
