Description
The Automotive Ethernet PHY IP Core is a 100M Ethernet PHY IP. Boasting a BroadR-Reach™ feature compatible with 100BaseT1 operations. It is a highly integrated single chip for 10/100 Ethernet application supporting 10BASE-T, 100BASE-TX, 100BASE-T1 operation. The IP connects MAC layer by GMII (Giga Media Independent Interface) or RGMII defined by IEEE 802.3ab, including the Physical Coding Sub-layer (PCS), Physical Medium Attachment Layer (PMA), Twisted Pair Physical Medium Dependent Sub-layer (TP-PMD, 100BASE-TX only).
Features
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IEEE 802.3-2008, IEEE 802.3az fully standards compliant
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IEEE 1588-2008 support
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BroadR-Reach™ support (100BaseT1)
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Dual port MAC interface:
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- GMII (10/100/1000BASE-T)
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- MII (10/100BASE-T).
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Auto-negotiation support
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Automatic detection and correction of pair
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swaps
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(Auto-MDIX), pair skew and pair polarity
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6 different operating modes:
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- 1000BASE-T Full Duplex and Half Duplex
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- 100BASE-TX/100BaseT1 Full and Half Duplex
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- 10BASE-T Full Duplex and Half Duplex
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Management interface
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Baseline wander compensation
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On-chip transmit wave-shaping
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On-chip hybrid circuit
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10KB jumbo frames
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Internal, external and remote loop back
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Hardware configuration for default operation
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Power down mode, interrupt support
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IEEE 1500 support for SoC testing integration
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LED indication: link mode, status, speed, activity, and collision
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Silicon Proven in ST 28nm FDSOI
Deliverables
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Verilog behaviour model (A) for simulation
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Liberty (.db/.lib) for synthesis, STA, and equivalence
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checking
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CTL / CTLDB for DFT
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SPF — Standard Test Interface Language (STIL)
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Procedure File — for ATPG
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LEF for APR
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CDL for LVS connection
