Description
The UART Whitebox IP is a configurable serial communication controller supporting full-duplex transmit and receive operation, programmable baud rates, flexible character formats, deep FIFOs, modem control, hardware and software flow control, prioritized interrupts, and comprehensive error reporting. Compatibility with widely used 16x50 UART software models simplifies integration into existing systems. The technology-independent RTL can be customized for the required FIFO depth, host bus, register map, and target ASIC or FPGA platform.
Features
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Full-duplex asynchronous transmitter and receiver
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Software-compatible with common 16x50 UART families
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Supports UART and FIFO operating modes
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Separate transmitter and receiver FIFOs
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Standard 128-byte FIFOs, configurable to larger depths
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Supports 5-, 6-, 7-, 8-, and 9-bit characters
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Programmable parity and one, 1.5, or two stop bits
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Programmable baud-rate generator and clock prescaler
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RTS/CTS and DTR/DSR hardware flow control
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XON/XOFF software flow control
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Modem-control and status signals
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Prioritized transmitter, receiver, status, and modem interrupts
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Break, parity, framing, and overrun-error detection
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Internal diagnostic and loopback modes
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Fully synthesizable Whitebox RTL with configurable bus wrappers
Deliverables
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Detailed Datasheet
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Verilog behaviour model (A) for simulation
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Liberty (.db/.lib) for synthesis, STA, and equivalence
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checking
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CTL / CTLDB for DFT
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SPF — Standard Test Interface Language (STIL)
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Procedure File — for ATPG
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LEF for APR
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CDL for LVS connection
