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MIPI D-PHY v1.1 Rx Whitebox IP in ST 28FDSOI

Description

The MIPI D-PHY v1.1 Rx Whitebox IP delivers a silicon-proven receiver solution for SoCs incorporating MIPI camera, imaging, and display interfaces. Developed in ST 28FDSOI technology, the PHY supports MIPI CSI-2 and MIPI DSI applications and connects to the associated receiver controller through a standard PPI interface. Its forwarded-clock architecture supports data reception at up to 1.5 Gbps per lane, Low-Power communication at up to 10 Mbps, and configurations comprising one clock lane and up to four data lanes. High-Speed, Escape, and Ultra-Low-Power operating modes help balance interface bandwidth with system power requirements.
 
The Whitebox licensing model provides customers with extensive control over the PHY design. Unlimited usage and full modification rights enable the IP to be customized for specific SoC requirements, reused across multiple chip programs, maintained internally, and migrated to alternative process technologies. By combining proven ST 28FDSOI silicon with source-level and design-database access, the IP offers a flexible foundation for long-term camera, display, multimedia, automotive, consumer, and IoT product development.

Features

  • Compliant with the MIPI Alliance D-PHY Specification v1.1
  • Receiver PHY for MIPI CSI-2 camera and MIPI DSI display applications
  • Supports source-synchronous operation with a dedicated forwarded clock
  • Supports High-Speed reception at up to 1.5 Gbps per data lane
  • Supports Low-Power asynchronous signalling at up to 10 Mbps
  • Supports High-Speed, Low-Power, Escape, and
  • Ultra-Low-Power operating modes
  • Supports one clock lane and up to four data lanes
  • Scalable single-lane and multi-lane configurations
  • Standard MIPI PPI interface for connection to
  • compatible CSI-2 and DSI receiver controllers
  • Analog front end for MIPI electrical-level signal reception
  • Digital back end for lane management and I/O control
  • Low-latency transitions between High-Speed and Low-Power operating states
  • High noise immunity and high jitter tolerance for
  • reliable camera and display connectivity
  • Low-power architecture suitable for bandwidthintensive multimedia applications
  • Available under a Whitebox licensing model
  • Unlimited usage rights across multiple SoCs and product derivatives
  • Full modification and application-specific customization rights
  • Enables independent maintenance and derivative development
  • Supports porting and optimization for other process technologies
  • Source and complete design-database technology transfer
  • Silicon-proven in ST 28FDSOI

Deliverables

  • Verilog behaviour model (A) for simulation
  • Liberty (.db/.lib) for synthesis, STA, and equivalence
  • checking
  • CTL / CTLDB for DFT
  • SPF — Standard Test Interface Language (STIL)
  • Procedure File — for ATPG
  • LEF for APR
  • CDL for LVS connection
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