Description
The DP 1.2 Tx Whitebox Controller IP provides a configurable DisplayPort source for SoCs and FPGAs requiring video and audio transmission over as many as four HBR2 lanes. It manages the DisplayPort main link, AUX interface, Hot-Plug Detect, link training, framing, 8b/10b encoding, scrambling, transfer units, and display-capability access. The technology-independent Whitebox RTL supports full architectural customization and unrestricted reuse across consumer, computing, automotive, industrial, and embedded-display products.
Features
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Designed for DisplayPort 1.2 transmitter applications
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Supports one-, two-, and four-main-link-lane configurations
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Supports RBR, HBR, and HBR2 data rates
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Main-link, AUX-channel, and Hot-Plug Detect support
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Full DisplayPort link-training sequence
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Supports default and enhanced framing 8b/10b channel encoding
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Programmable data scrambling and scrambler reset
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Transfer-unit generation and symbol stuffing
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Supports interlaced and progressive video streams
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Video, audio, and secondary-data packet transmission
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I2C-over-AUX, EDID, and DPCD access
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Configurable SST and MST operation
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Fully synthesizable Whitebox RTL with complete modification rights
Deliverables
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Detailed Datasheet
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Verilog behaviour model (A) for simulation
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Liberty (.db/.lib) for synthesis, STA, and equivalence
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checking
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CTL / CTLDB for DFT
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SPF — Standard Test Interface Language (STIL)
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Procedure File — for ATPG
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LEF for APR
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CDL for LVS connection
