Description
The 15G SerDes Whitebox IP delivers silicon-proven, multi-rate serial connectivity for networking, communication, data-processing, and chip-to-chip SoCs. Operating from 1.125 Gbps to 15 Gbps, the ST 28FDSOI transceiver supports CEI-6G/11G reach profiles, XFI/SFI, XAUI/CAUI, SGMII, QSGMII, and CR4 applications. Advanced Tx FIR and Rx DFE equalization, together with multi-rate clock distribution, helps maintain link margin across a range of electrical channels.
The Whitebox model gives semiconductor companies control over both integration and future development. The SerDes can be modified, optimized for customer-specific PPA and channel targets, reused without per-project restrictions, maintained internally, and ported to another process technology.
Features
-
Multi-protocol transmitter and receiver SerDes PHY
-
Supports serial data rates from 1.125 Gbps to 15 Gbps
-
Supports CEI-6G and CEI-11G short-, medium-, and long-reach profiles
-
Supports XFI and SFI interfaces
-
Supports XAUI and CAUI applications
-
Supports SGMII and QSGMII
-
Supports CR4 applications
-
Scalable architecture for single-lane and multilane integration
-
Modular data-slice and clock-slice platform
-
Receiver linear equalization
-
Four-tap receiver decision-feedback equalizer
-
Six-tap transmitter FIR equalizer
-
Programmable transmit pre-emphasis and deemphasis
-
Dual clock-distribution architecture for multirate operation
-
Optimized for low-power, low-latency serial connectivity
-
Whitebox license with unlimited use, full
-
modification, design reuse, and process-porting rights
-
Silicon-proven in ST 28FDSOI
Deliverables
-
Verilog behaviour model (A) for simulation
-
Liberty (.db/.lib) for synthesis, STA, and equivalence
-
checking
-
CTL / CTLDB for DFT
-
SPF — Standard Test Interface Language (STIL)
-
Procedure File — for ATPG
-
LEF for APR
-
CDL for LVS connection
