Description
The eDP 1.4 Tx Whitebox PHY IP in ST 28FDSOI delivers low-power embedded-display connectivity while also supporting DisplayPort 1.2a applications. Its scalable one-, two-, or four-lane architecture operates at RBR, HBR, and HBR2 rates and includes an AUX channel, shared PLL, per-lane power control, spread-spectrum clocking, programmable FFE, and embedded BIST. Full Whitebox design access enables unrestricted reuse, electrical customization, internal maintenance, and migration to future process technologies.
Features
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Combined eDP 1.4 and DisplayPort 1.2a transmitter PHY
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Supports one-, two-, and four-main-link-lane configurations
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Supports RBR at 1.62 Gbps per lane
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Supports HBR at 2.7 Gbps and HBR2 at 5.4 Gbps per lane
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Integrated half-duplex bidirectional AUX channel
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Supports 10-bit or 20-bit per-lane parallel interfaces
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AC-coupled main-link transmitter
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Shared PLL for all enabled main-link lanes
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Individual power-down control for each lane
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Supports spread-spectrum clock generation
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Programmable transmitter swing and preemphasis
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Programmable two-tap transmit FFE
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Embedded BIST and test support
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Whitebox licensing with full customization and
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porting rights Detailed Da
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Silicon-proven in ST 28FDSOI
Deliverables
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Detailed Datasheet
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Verilog behaviour model (A) for simulation
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Liberty (.db/.lib) for synthesis, STA, and equivalence
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checking
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CTL / CTLDB for DFT
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SPF — Standard Test Interface Language (STIL)
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Procedure File — for ATPG
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LEF for APR
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CDL for LVS connection
