Description
The DisplayPort 1.2 Tx Whitebox PHY IP is a silicon-proven ST 28FDSOI transmitter supporting up to four HBR2 lanes and 21.6 Gbps of aggregate raw bandwidth. Its architecture includes a bidirectional AUX channel, shared PLL, programmable voltage swing and pre-emphasis, spread-spectrum clocking, individual lane power controls, and embedded test features. The PHY is suitable for monitors, televisions, graphics processors, automotive displays, docking devices, and multimedia SoCs requiring reusable DisplayPort connectivity.
Features
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Designed for DisplayPort 1.2 transmitter applications
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Supports one-, two-, and four-main-link-lane configurations
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Supports RBR at 1.62 Gbps per lane
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Supports HBR at 2.7 Gbps and HBR2 at 5.4 Gbps per lane
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Aggregate main-link bandwidth of up to 21.6 Gbps
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Integrated bidirectional AUX channel
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Supports 10-bit or 20-bit per-lane parallel interfaces
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AC-coupled differential main-link outputs
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Shared PLL and clock-generation architecture
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Individual lane-enable and power-down controls
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Programmable voltage swing and pre-emphasis
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Spread-spectrum clocking support
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Embedded BIST and loopback-test functions
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Whitebox license with modification, reuse, and porting rights
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Silicon-proven in ST 28FDSOI
Deliverables
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Detailed Datasheet
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Verilog behaviour model (A) for simulation
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Liberty (.db/.lib) for synthesis, STA, and equivalence
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checking
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CTL / CTLDB for DFT
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SPF — Standard Test Interface Language (STIL)
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Procedure File — for ATPG
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LEF for APR
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CDL for LVS connection
