Description
The QSPI Whitebox IP is a flexible serial-memory and peripheral controller supporting SPI, Dual-SPI, and Quad-SPI transfer modes. It provides programmable clock polarity, phase, and baud rate, Flash-command execution, execute-in-place access, 32-bit addressing, configurable FIFOs, DMA, interrupt handling, and APB, AHB, or AXI connectivity. The process-independent Whitebox RTL can be customized for different Flash devices, memory maps, transfer widths, performance targets, and SoC architectures.
Features
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Supports Single-SPI, Dual-SPI and Quad-SPI operation
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Configurable controller and peripheral operating modes
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Full-duplex transfer in Single-SPI mode
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Supports all four CPOL and CPHA transfer formats
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Programmable serial-clock and baud-rate generation
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Configurable 8-, 16-, and 32-bit system-data widths
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Built-in programmable Flash-command execution
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Supports up to 32-bit Flash addressing
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Execute-in-place functionality
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Configurable transmit and receive FIFOs
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DMA interface support
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Supports multiple external SPI devices
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APB, AHB, AXI, or custom host-interface options
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Interrupt and system-error reporting
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Fully synthesizable Whitebox RTL with unrestricted customization
Deliverables
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Detailed Datasheet
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Verilog behaviour model (A) for simulation
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Liberty (.db/.lib) for synthesis, STA, and equivalence
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checking
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CTL / CTLDB for DFT
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SPF — Standard Test Interface Language (STIL)
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Procedure File — for ATPG
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LEF for APR
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CDL for LVS connection
