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T2M › SerDes › 112G Very-Short-Reach SerDes Whitebox IP in TSMC 5FF

112G Very-Short-Reach SerDes Whitebox IP in TSMC 5FF

Description

The 112G SerDes Whitebox IP provides ultra-high-bandwidth connectivity for very-short-reach links in chiplet systems, AI accelerators, networking ASICs, high-performance computing devices, optical modules, and co-packaged-optics platforms. Silicon-proven in TSMC 5FF, the multi-rate architecture supports up to 112 Gbps per lane using PAM4 and lower data rates using NRZ. Adaptive transmit and receive equalization, robust CDR, autonomous link adaptation, and on-chip diagnostic functions enable efficient integration and rapid link bring-up.
 
The Whitebox license allows customers to optimize the design for their package and channel, reduce power or area for VSR use, reuse the architecture across multiple programs, maintain it internally, and migrate it to another advanced process node.

Features

  • High-performance transmitter and receiver SerDes PHY
  • Supports data rates of up to 112 Gbps per lane
  • Supports 56–112 Gbps PAM4 operating modes
  • Supports lower-rate NRZ operation from 1 Gbps to 56 Gbps
  • Optimized for very-short-reach electrical channels
  • Suitable for chip-to-chip, die-to-die, opticalmodule, and co-packaged-optics interfaces
  • Scalable single-lane and multi-lane configurations
  • Programmable multi-tap transmitter equalization
  • Adaptive DSP-based receiver equalization
  • Robust baud-rate clock and data recovery
  • Automatic receiver start-up and dynamic adaptation
  • Integrated control processor or microcontroller
  • MDIO-style configuration and status interface
  • Built-in PRBS generation and checking
  • BIST and line/system loopback modes
  • BER estimation, receiver eye statistics, and channel-quality monitoring
  • Independent rate, reset, and power control for each lane
  • Small-area and low-power architecture for high port density
  • Whitebox license with unlimited usage, full
  • modification, derivative-development, and process-porting rights
  • Silicon-proven in TSMC 5FF
Deliverables
  • Verilog behaviour model (A) for simulation
  • Liberty (.db/.lib) for synthesis, STA, and equivalence
  • checking
  • CTL / CTLDB for DFT
  • SPF — Standard Test Interface Language (STIL)
  • Procedure File — for ATPG
  • LEF for APR
  • CDL for LVS connection
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