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USB 2.0 OTG Whitebox PHY IP in ST 28FDSOI

Description

The USB 2.0 OTG Whitebox PHY IP is a silicon-proven physical-layer solution developed for SoCs requiring flexible USB Host, Device, or dual-role OTG connectivity. Implemented in ST 28FDSOI technology, the IP supports both single-port and multi-port architectures, allowing the USB subsystem to be configured according to the connectivity requirements of the target SoC. It supports USB High-Speed operation at up to 480 Mbps while maintaining compatibility with Full-Speed at 12 Mbps and Low-Speed at 1.5 Mbps.
 
Offered under a whitebox licensing model, the IP provides unlimited usage and full modification rights. Customers can customize the design for application-specific requirements, reuse it across multiple chip programs, create derivative implementations, and port the IP to other semiconductor process technologies. The combination of silicon-proven implementation and design-level access gives development teams greater control over integration, optimization, maintenance, and long-term USB IP reuse.
 
Primary SEO phrase: USB 2.0 OTG Whitebox PHY IP
Supporting phrases: ST 28FDSOI USB PHY, silicon-proven USB 2.0 PHY IP, multi-port USB PHY IP, USB Host and Device PHY

Features

  • Designed for compliance with USB 2.0 and USB 1.1 specifications
  • Supports High-Speed at 480 Mbps, Full-Speed at
  • 12 Mbps, and Low-Speed at 1.5 Mbps
  • Supports USB Host, Device, and dual-role OTG applications
  • Compatible with USB 2.0 OTG function controllers
  • Supports single-port and multi-port configurations
  • UTMI+ Level 3 interface for connection to the USB controller
  • Supports 8-bit at 60 MHz or 16-bit at 30 MHz parallel controller interfaces
  • Integrated transmitter serialization and receiver deserialization
  • Integrated clock recovery and data recovery for received USB traffic
  • NRZI encoding and bit-stuffing for transmitted data
  • NRZI decoding and bit-unstuffing for received data
  • SYNC and End-of-Packet generation for transmitted packets
  • SYNC and End-of-Packet detection for received packets
  • Supports USB reset, suspend, and resume signaling detection
  • Supports USB suspend mode and remotewakeup operation
  • Supports USB 2.0 High-Speed identification and detection
  • Supports High-Speed host-disconnect detection
  • Supports protocol-required DP/DM pull-up and pull-down terminations
  • Low-power architecture suitable for embedded and portable SoC applications
  • Silicon-proven in ST 28FDSOI
  • Available under a whitebox licensing model
  • Unlimited usage rights across multiple projects and product derivatives
  • Full rights to modify, customize, maintain, and enhance the IP
  • Full rights to port the IP to other process technologies.
Deliverables
  • Detailed Datasheet
  • Verilog behaviour model (A) for simulation
  • Liberty (.db/.lib) for synthesis, STA, and equivalence
  • checking
  • CTL / CTLDB for DFT
  • SPF — Standard Test Interface Language (STIL)
  • Procedure File — for ATPG
  • LEF for APR
  • CDL for LVS connection
Request Datasheet