Description
The HDMI–DP Rx Combo Whitebox Controller IP enables SoCs and FPGAs to receive HDMI 1.4b or DisplayPort 1.2 video and audio through a unified, configurable digital architecture. It supports HDMI packet and InfoFrame processing together with DisplayPort link training, AUX communication, lane alignment, EDID access, and rates through HBR2. Its technology-independent Whitebox RTL can be customized for product-specific interfaces, reused across multiple designs, and integrated with a matching HDMI–DP combo receiver PHY.
Features
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Combined HDMI 1.4b and DisplayPort 1.2 receiver controller
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Selectable HDMI sink and DisplayPort sink operating modes
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Supports DVI-compatible reception in HDMI mode
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Supports DisplayPort RBR, HBR, and HBR2 rates
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Supports one-, two-, and four-lane DisplayPort configurations
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Main-link, AUX-channel, and Hot-Plug Detect management
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DisplayPort link training, lane alignment, and descrambling
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Supports default and enhanced DisplayPort framing
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HDMI TMDS decoding and packet extraction
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Supports RGB and YCbCr video data formats
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Supports HDMI audio and InfoFrame extraction
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DDC, EDID, and DPCD-access support
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Configurable application and register interfaces
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Fully synthesizable Whitebox RTL with modification and reuse rights
Deliverables
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Detailed Datasheet
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Verilog behaviour model (A) for simulation
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Liberty (.db/.lib) for synthesis, STA, and equivalence
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checking
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CTL / CTLDB for DFT
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SPF — Standard Test Interface Language (STIL)
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Procedure File — for ATPG
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LEF for APR
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CDL for LVS connection
