Description
The HDMI–DP Rx Combo Whitebox PHY IP integrates HDMI 1.4b and DisplayPort 1.2 receiver connectivity into a common silicon-proven ST 28FDSOI implementation. The PHY supports HDMI bandwidth up to 10.2 Gbps and DisplayPort HBR2 operation up to 5.4 Gbps per lane across four main-link lanes. By combining both display interfaces with AUX-channel support, embedded test features, and full Whitebox modification rights, the IP provides a versatile foundation for monitors, televisions, projectors, automotive displays, docking products, and multimedia SoCs.
Features
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Combined HDMI 1.4b and DisplayPort 1.2 receiver PHY
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Supports selectable HDMI and DisplayPort operating modes
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Compatible with HDMI and DVI receiver applications
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Supports three HDMI TMDS data channels and one clock channel
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HDMI aggregate bandwidth of up to 10.2 Gbps
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Supports one, two, or four DisplayPort main-link lanes
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Supports DisplayPort RBR at 1.62 Gbps per lane
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Supports HBR at 2.7 Gbps and HBR2 at 5.4 Gbps per lane
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DisplayPort aggregate bandwidth of up to 21.6 Gbps
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Integrated bidirectional DisplayPort AUXchannel interface
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Supports HDMI 3D video through 1080p at 60 Hz
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At-speed BIST and loopback-test support
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Whitebox license with full customization and process-porting rights
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Silicon-proven in ST 28FDSOI
Deliverables
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Detailed Datasheet
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Verilog behaviour model (A) for simulation
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Liberty (.db/.lib) for synthesis, STA, and equivalence
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checking
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CTL / CTLDB for DFT
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SPF — Standard Test Interface Language (STIL)
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Procedure File — for ATPG
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LEF for APR
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CDL for LVS connection
