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MIPI DSI v1.1 Tx Whitebox Controller IP

Description

The MIPI DSI v1.1 Tx Whitebox Controller IP provides a flexible and power-efficient display-interface solution for SoCs used in mobile devices, automotive infotainment systems, instrument clusters, wearables, IoT products, and consumer electronics. The controller transfers video, display commands, and control information from an application processor or graphics subsystem to a compatible display panel through a MIPI D-PHY interface. It supports programmable one-, two-, or four-data-lane configurations with data rates of up to 1.5 Gbps per lane, enabling scalable bandwidth for a range of display resolutions and refresh-rate requirements.
 
Support for Command Mode, Video Mode, Burst and Non-Burst transmission, multiple virtual channels, and commonly used 16-, 18-, and 24-bit-per-pixel interfaces allows the controller to address a broad range of embedded display architectures. Packet generation, ECC and CRC handling, reverse Low-Power communication, clock-mode control, and comprehensive error reporting help simplify integration with compatible MIPI D-PHY transmitters and display peripherals.
 
Supplied under a Whitebox license, the controller provides unlimited usage and full design-modification rights. Semiconductor companies can customize the RTL, adapt system interfaces, reuse the IP across multiple products, maintain the implementation internally, and port the controller to other foundries or process nodes. This flexible technology-transfer model gives customers greater ownership of their display-interface roadmap while reducing dependence on fixed, project-specific licensing.

Features

  • Designed for compliance with the MIPI DSI Specification v1.1
  • Host-side MIPI DSI transmitter controller
  • Compatible with a MIPI D-PHY transmitter
  • Supports one-, two-, or four-data-lane configurations
  • Supports data rates of up to 1.5 Gbps per lane
  • Supports continuous and non-continuous clock modes
  • Supports Command Mode and Video Mode operation
  • Supports Burst and Non-Burst video transmission
  • Supports Non-Burst Mode with Sync Pulse or Sync Event
  • Supports forward High-Speed and bidirectional Low-Power communication
  • Supports Bus Turn-Around for peripheral-tohost communication
  • Configurable support for up to four virtual channels
  • Supports short and long packets, MIPI DCS commands, and generic packets
  • Supports RGB565, RGB666, and RGB888 display formats
  • Packet-header ECC and long-packet payload CRC generation
  • Protocol and D-PHY error detection and reporting
  • Modular architecture with separated clock domains and clock-gating support
  • Whitebox license with unlimited usage, full modification, derivative-development, and process-porting rights

Deliverables

  • Verilog behaviour model (A) for simulation
  • Liberty (.db/.lib) for synthesis, STA, and equivalence
  • checking
  • CTL / CTLDB for DFT
  • SPF — Standard Test Interface Language (STIL)
  • Procedure File — for ATPG
  • LEF for APR
  • CDL for LVS connection
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