Description
The MIPI CSI-2 Rx v1.1 Controller Whitebox IP provides a flexible camera-interface solution for SoCs used in mobile devices, automotive imaging, industrial vision, IoT products, surveillance systems, and consumer electronics. Supporting one, two, or four D-PHY data lanes at up to 1.5 Gbps per lane, the controller receives and decodes CSI-2 image streams across a broad selection of YUV, RGB, RAW, and user-defined data formats. Configurable Pixel or AXI application interfaces simplify connection to image signal processors, video pipelines, memories, and other SoC subsystems.
Its Whitebox license gives development teams full control over the controller source and implementation. The design can be modified for application-specific requirements, reused without per-project restrictions, maintained internally, and ported to alternative semiconductor processes.
Features
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Compliant with the MIPI CSI-2 Specification v1.1
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Compatible with MIPI D-PHY v1.1
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Programmable one-, two-, or four-data-lane configuration
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Supports continuous and non-continuous DPHY clock modes
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Supports data rates of up to 1.5 Gbps per lane
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Supports YUV420 and YUV422 formats with 8-bit and 10-bit component depths
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Supports RGB888, RGB666, RGB565, RGB555, and RGB444 formats
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Supports RAW6, RAW7, RAW8, RAW10, RAW12, and RAW14 image data
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Supports user-defined CSI-2 data types 64-bit pixel-data alignment
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Selectable register configuration through a generic parallel interface
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Configurable application-side Pixel or AXI interface
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Modular and layered controller architecture
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Clearly separated clock domains with extensive clock-gating support
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Active-low asynchronous reset support
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Whitebox license with unlimited usage, full
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modification, derivative-development, and process-porting rights.
Deliverables
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Verilog behaviour model (A) for simulation
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Liberty (.db/.lib) for synthesis, STA, and equivalence
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checking
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CTL / CTLDB for DFT
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SPF — Standard Test Interface Language (STIL)
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Procedure File — for ATPG
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LEF for APR
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CDL for LVS connection