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MIPI D-PHY v1.1 Tx Whitebox IP in ST 28FDSOI

Description

The MIPI D-PHY v1.1 Tx Whitebox IP provides a silicon-proven, low-power physical-layer transmitter for embedded camera and display interfaces. Developed for ST 28FDSOI technology, the PHY enables reliable connectivity between MIPI CSI-2 or DSI transmitter controllers and compatible image sensors, displays, bridge devices, and other multimedia peripherals. It supports forwarded-clock operation, a standard MIPI PPI controller interface, one clock lane, and up to four high-speed data lanes operating at up to 1.5 Gbps per lane. Low-Power, Escape, and Ultra-Low-Power modes enable efficient operation across active and power-sensitive system states.
 
The Whitebox license gives customers greater ownership and flexibility than a conventional fixed-configuration PHY license. Unlimited usage and full modification rights allow the design to be reused across multiple SoCs, customized for product-specific requirements, maintained internally, and ported to alternative foundries or process nodes. Combining a silicon-proven ST 28FDSOI implementation with extensive design control makes this MIPI D-PHY Tx IP suitable for long-term mobile, automotive, IoT, imaging, consumer-electronics, and display-platform development.

Features

  • Compliant with the MIPI Alliance D-PHY Specification v1.1
  • Transmitter PHY for MIPI CSI-2 and MIPI DSI applications
  • Supports Forwarded Clock Mode
  • Supports High-Speed data transmission at up to 1.5 Gbps per data lane
  • Supports Low-Power asynchronous signalling at up to 10 Mbps
  • Supports High-Speed, Low-Power, Escape, and
  • Ultra-Low-Power operating modes
  • Supports one dedicated clock lane and up to four data lanes
  • Supports scalable single-lane and multi-lane implementations
  • Standard MIPI PPI interface for connection to compatible CSI-2 and DSI controllers
  • Supports low-latency transitions between HighSpeed and Low-Power operating states
  • Low-power serial architecture suitable for camera and display subsystems
  • Designed for low electromagnetic interference,
  • high noise immunity, and high jitter tolerance
  • Suitable for mobile, automotive, IoT, consumerelectronics, imaging, display, AR, and VR applications
  • Available under a Whitebox licensing model
  • Unlimited usage rights across multiple SoCs,
  • projects, and product derivatives
  • Full modification and application-specific customization rights
  • Supports independent maintenance and derivative development
  • Full rights to port and optimize the IP for other process technologies
  • Silicon-proven in ST 28FDSOI

Deliverables

  • Verilog behaviour model (A) for simulation
  • Liberty (.db/.lib) for synthesis, STA, and equivalence
  • checking
  • CTL / CTLDB for DFT
  • SPF — Standard Test Interface Language (STIL)
  • Procedure File — for ATPG
  • LEF for APR
  • CDL for LVS connection
 
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