Description
The MIPI DigRF v1.0 Whitebox IP provides silicon-proven Tx and Rx physical-layer connectivity between RF transceiver devices and baseband processors. Implemented in ST 28FDSOI, the PHY is designed for the low-power, low-latency, and low-EMI transfer of radio sample data and control traffic in cellular and wireless SoCs. Its bidirectional architecture supports the integration of RF and modem subsystems while reducing interface pin count and accommodating scalable transmit and receive configurations.
Through the Whitebox license, customers obtain extensive control over the PHY implementation. The design may be modified for proprietary radio architectures, reused across several modem products, maintained internally, and ported or optimized for another process technology.
Features
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Designed for MIPI DigRF applications
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Integrated transmitter and receiver PHY functions
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Provides physical connectivity between RFIC
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and baseband or modem processors
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MIPI M-PHY-based physical transport architecture
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Supports transport of RF sampled-data and control traffic
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Low-latency operation for real-time radio interfaces
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Fast link start-up capability
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Optimized for low interface power consumption
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Low-electromagnetic-interference signalling architecture
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Reduced interface pin count
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Scalable architecture for multiple transmit and receive signal paths
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Supports reliable link operation and protocollevel error protection
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Suitable for multi-mode and multi-band wireless platforms
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Applicable to cellular modems, RF transceivers, and connected-device SoCs
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Whitebox license with unlimited usage and complete modification rights
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Supports independent maintenance, derivative
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development, and process migration
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Silicon-proven in ST 28FDSOI
Deliverables
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Verilog behaviour model (A) for simulation
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Liberty (.db/.lib) for synthesis, STA, and equivalence
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checking
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CTL / CTLDB for DFT
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SPF — Standard Test Interface Language (STIL)
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Procedure File — for ATPG
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LEF for APR
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CDL for LVS connection
