Production Proven, Complex Semiconductor IP Cores

IP Cores


T2M MIPI MIPI M-PHY v3.1 IP

MIPI M-PHY v3.1 IP

Description and Features

The MIPI M-PHY Gear 3 IP is compliant with the latest MIPI Feature Storage IP Solution SerDes PHY Product Brief Alliance M-PHY v3.0 Specification, UniPro v1.8 Specification, and Universal Flash Storage (UFS) v3.0 Specification. A serial interface technology with high bandwidth capabilities and supports HS Gear3 rates up to 5.8Gbps, which is particularly developed for mobile applications to obtain low pin count combined with very good power efficiency. The MIPI M-PHY Gear 3 IP compliant to the RMMI interface which allows UniPro controller and UFS Controller.

The MIPI M-PHY provides robust testability by low cost Build-In-Self-Test (BIST), and receiver eye data monitoring and debugging function for embedded system.

 MIPI-M-PHY-v3.1-silicon-proven-ip-core-supplier-in-china 

 

Features
  • Compliant with M-PHY Spec 3.0
  • Support HS-MODE Gear3(A/B) with data rate up to 5.8Gb/s, and backward compatible
  • Support LS-MODE PWM-G1 to PWM-G4 with data rate up to 72Mb/s
  • Support reference clock frequency with 19.2/26/38.4/52MHz defined in UFS spec
  • Support RMMI interface for Type-I application
  • Receiver eye open for monitoring and debugging
  • Support Build In-Self Test(BIST) for low cost CP/FT

Deliverables

  • Application Note / User Manual
  • Behavior model, and protected RTL codes
  • Protected Post layout netlist and Standard Delay Format (SDF)
  • Library (LIB)
  • Frame view (LEF)
  • Metal GDS (GDSII)
  • Test patterns and Test Documentation

Benefits

  • 2-tap DFE, CTLE, 2-tap FFE
  • Channel Loss? >14dB @6GHz Nyquist
  • Low HS-Gear4 operation current and low standby current
  • Competitive IP PPA leading in the market