USB 3.1 Type-C PHY IP

Description and Features

USB 3.1Type-C PHY IP iis a high performance high speed SERDES IP designed for chips that perform high bandwidth data communication while operating at low power consumption. USB 3.1Type-C PHY IP is a dedicate design for USB3.1 type-C application. USB 3.1 Type C PHY IP is a pure analog IP that perform serialization and deserialization only, a dedicate PCS can be provided together with PHY to accomplish functions of different application, including elastic buffer, scramble/de-scramble, data encoding/decoding, PRBS generation/checking, registers control and testing. PCS is provided as either hard or soft macro based on customer’s request, the specification of PCS will also be provided separately PHY functionality is verified in NC-Verilog simulation software using test bench written in Verilog HDL.

Features

• Support half rate mode (5Gbps) and full rate mode (10Gbps)
• Tolerate max +/-7000ppm input frequency offset
• 32bit/40bit selectable parallel data bus
• Programmable transmit amplitude
• 3 taps/2 taps selectable FFE
• Receiver CTLE and One-tap perspective DFE
• Build in self-test with PRBS7/31 pattern generation and checker for production test
• Integrated on-die termination resistors
• Support receiver detection
• Support LFPS signal generation and detection
• Support Spread Spectrum clock generation and receiving
• Flexible reference clock frequency
• Do not need any external component
• ESD: HBM/MM/CDM/Latch Up 2000V/200V/500V/100mA
• Metal Layer:M1~M7+RDL
• Core Voltage: 1.1V
• IO Voltage: 3.3V

Deliverables

• GDSII & layer map
• Place-Route views (.LEF)
• Liberty library (.lib)
• Verilog behavior model
• Netlist & SDF timing
• Layout guidelines, application notes
• LVS/DRC verification reports