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Elevate Your Display and Camera SOC Capabilities with our latest Silicon Proven MIPI C-D Combo Tx/Rx PHY and DSI Controller IP Cores

05 Feb, 2024

T2MIP, the world's leading independent semiconductor IP cores provider and technology experts, is pleased to announce the immediate license availability of its partner's MIPI Alliance-approved semiconductor effective MIPI C-PHY/D-PHY Tx & Rx and DSI Controller IP cores provide a high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral devices for camera, mobile, automotive, AI, and IoT applications.
 
MIPI D-PHY stands as a prevalent serial interface technology, widely embraced in smartphones and other multimedia-capable mobile devices. In pursuit of enhancing throughput across constrained channels, the C-PHY has been developed, achieving a commendable 2.28 bits per symbol across a three-wire trio. As a noteworthy contributor to the MIPI Alliance and a prominent provider of Interface IP, our vendor partner offers a proven, energy-efficient, and cost-effective MIPI C-PHY/D-PHY Tx & Rx and DSI Controller IP cores combination IP across diverse process nodes. This versatile solution allows users to configure the PHY into either D-PHY mode or C-PHY mode, catering to a range of applications with the same PHY. Furthermore, it adheres to the PPI interface standards, facilitating seamless integration with upstream controllers for Camera Serial Interface (CSI-2) and Display Serial Interface (DSI) protocols.
 
 
Wi-Fi 6 And Wi-Fi 6E SoCs
 
The MIPI DSI (Display Serial Interface) controller IP plays a crucial role in conjunction with a MIPI C/D (C-PHY/D-PHY) combo PHY IP, contributing to a comprehensive interface solution for multimedia applications, particularly in mobile devices. The MIPI DSI controller IP is responsible for managing the communication between the host processor and the display device. It interprets the video data from the processor and formats it into a stream that is compatible with the MIPI D-PHY or C-PHY interface. The DSI controller ensures the proper synchronization, timing, and packetization of data, allowing for efficient and high-speed transmission to the display. When integrated with a MIPI C/D combo PHY IP, the DSI controller collaborates with the physical layer functions provided by the C-PHY and D-PHY components of the combo PHY IP. The C-PHY is designed to handle high-speed data transmission over multiple lanes, supporting complex modulation schemes to achieve higher throughput.
 
Our versatile MIPI C-PHY/D-PHY Tx & Rx and DSI Controller IP cores interface solution supports the MIPI DSI and CSI-2 protocols, accommodating high-speed (HS) data rates of up to 6Gbps (6Gsps) per lane (per trio). With the flexibility to operate in D-PHY mode featuring one clock lane and up to four data lanes, it also supports C-PHY mode with up to three trios for TX and four trios for RX. Additionally, the interface offers an extra RX mode with two sets of one clock lane and up to two data lanes. Notably, it supports a low-speed (LS) data rate of 10Mbps and ultra-low power modes, including Alternate Low-Power (ALP) mode. The inclusion of D-PHY swap functions for clock and data lanes, C-PHY swap functions for trios, and a stand-alone Built-In Self-Test (BIST) module for at-speed mass production testing further enhance its capabilities. This comprehensive solution has been certified with ASIL-B of ISO-26262, ensuring reliability and safety in automotive applications.
 
Availability: These IP Cores are available for immediate licensing. For more information on licensing options and pricing please drop a request / MailTo .
 
About T2M: T2MIP is the global independent semiconductor technology experts, supplying complex semiconductor IP Cores, Software, KGD and disruptive technologies enabling accelerated development of your Wearables, IOT, Communications, Storage, Servers, Networking, TV, STB and Satellite SoCs. For more information, please visit:on  www.t-2-m.com