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Implement Seamless DRAM Processing Speeds Utilizing Silicon Proven DDR4/LPDDR4/DDR3L Combo PHY IP Core In 12FFC Process Technology!!

05 Dec, 2022

T2MIP, the global independent semiconductor IP Cores provider & Technology experts, is pleased to announce the immediate availability of its partner’s DDR4/LPDDR4/DDR3L Combo PHY IP Core in 12FFC process nodes with matching DDR4 Combo Controller IP Core which is silicon proven and has been extracted from production chips. This IP Cores has had a great track of implementation on production chips by Chinese, European and American customers.
The DDR4/ DDR3L/ LPDDR4 Combo PHY IP Core provides an excellent processing data rate, and its low latency enables up to 3200Mbps throughput for high-speed RAM applications. The PHY IP Cores is compliant with the latest JEDEC standards and is silicon proven in 12FFC process technology and is designed for ease of integration and faster time-to-market for an ever in-demand market. This IP Cores can function as a standalone DDR4, LPDDR4 or DDR3L PHY IP cores according to the user’s requirement, boasting an area and power consumption numbers comparable to standard standalone DDR4 PHYs. Coupled with the matching DDR4/LPDDR4/DDR3L Combo Controller IP Cores or a standalone DDR4, LPDDR4 Controller IP Cores, this total solution works to achieve a flawless interfacing speed for DRAM functions on varied range of products.
The JEDEC standard compliant DDR4/ DDR3L/ LPDDR4 Combo PHY IP Core reaches a 3200Mbps throughput with a Maximum controller clock frequency of 400MHz resulting in maximum DRAM data rate of 3200Mbps and a compatible SSTL135/POD12/LVSTL Interface. It includes a data path width scale in 32-bit increment and Four modules for flexible configuration: CA/DQ_X16/DQ_X8/ZQ. The Combo PHY also enables a high degree of flexibility with a Programmable output impedance (DS) and on-die termination (ODT).
Additional support for ZQ calibration, support for 8 ranks, write-levelling, CBT and PHY internal VREFDQ for auto decision, can enable to handle Per-bit deskew in read and write datapath for an added level of control over the Physical layer and Link Layer.
The DDR4 Combo PHY IP cores along with the DDR4 Combo Controller IP cores has been used in semiconductor industry’s Enterprise computing, storage area networks, Embedded systems, Graphics devices and other Consumer Electronics..
In addition to DDR4 IP Cores, T2M ‘s broad silicon Interface IP Core Portfolio includes USB, HDMI, Display Port, MIPI (CSI, DSI, UniPro, UFS, Soundwire, I3C), PCIe, 10/100/1000 Ethernet, V by One, programmable SerDes, SD/eMMCs, Serial ATA and many more IP Cores, available in major Fabs in process geometries as small as 7nm. They can also be ported to other foundries and leading-edge processes nodes on request..
Availability: These Semiconductor Interface IP Cores are available for immediate licensing either stand alone or with pre-integrated Controllers and PHYs. For more information on licensing options and pricing please drop a request at / MailTo
About T2M: T2MIP is the global independent semiconductor technology experts, supplying complex semiconductor IP Cores, Software, KGD and disruptive technologies enabling accelerated development of your Wearables, IOT, Communications, Storage, Servers, Networking, TV, STB and Satellite SoCs. For more information, please visit: